7nm & 5nm VLSI Design Engineers

**Hiring: 7nm & 5nm VLSI Design Engineers | Advanced Node Development | FinFET Technology** We are expanding our advanced semiconductor R&D team and inviting applications from engineers ready to work on 7nm and 5nm technology node projects involving FinFET-based SoC development. • *Role Overview** Selected candidates will work on the complete RTL-to-GDSII implementation flow for advanced-node designs, focusing on high-performance, low-power digital SoCs using industry-standard EDA tools. • *Mandatory Prerequisites** Applicants must have: \* Strong understanding of RTL to GDSII flow \* Hands-on experience in 45nm and below VLSI design projects \* Solid knowledge of FinFET technology fundamentals \* Experience with advanced-node challenges: \* Timing closure \* IR drop and EM analysis \* DRC and LVS signoff \* Practical exposure to Cadence EDA tools: \* Cadence Virtuoso (Custom / Analog Layout) \* Cadence Genus (RTL Synthesis) \* Cadence Innovus (Physical Design) \* Cadence Tempus (STA and Signoff) \* Cadence Voltus (Power Analysis, IR/EM) \* Strong understanding of signoff methodologies and MCMM closure • *Important Requirements** \* Candidates must have hands-on experience with industry-standard tools (Cadence suite as listed above) \* Experience limited to open-source or free tools will not be considered \* Strong fundamentals in ASIC design flow and semiconductor concepts are mandatory \* Only candidates who have worked on 45nm or below technologies should apply • *Preferred Skills** \* Understanding of advanced-node constraints (7nm/5nm DFM, multi-patterning, variability) \* TCL scripting proficiency \* Experience in timing-driven PnR and low-power methodologies \* Exposure to AI-assisted physical design flows \* Strong debugging and analytical skills • *Who Should Apply** \* Engineers with experience in 45nm and below nodes who are looking to transition to 7nm and 5nm technologies \* Candidates with strong foundations in VLSI, ASIC design flow, and semiconductor physics \* Individuals interested in working on next-generation SoC architectures • *Location** • *Bangalore (On-site)** • *Interview Process** • *\* All interview rounds will be conducted in person; no virtual or online interviews will be arranged** • *\* Candidates currently residing in Bangalore will be given preference** • *\* Applicants from other locations must be willing to travel to Bangalore for the interview process** • *\* Candidates not willing to attend in-person interviews are advised not to apply** • *How to Apply** Interested candidates may share their CV and detailed project portfolio via LinkedIn message or email.