RTL (ASIC) Professionals
Digicomm Semiconductor
Bengaluru, Karnataka, IN Full–Time
- 4+ years of experience who will be responsible to taking ownership of our SPI interface and configuration register management.
- At least 2 Years/2 projects in ASIC RTL design. Pure FPGA RTL profiles will not be considered.
- The designer will take responsibility for modifying the existing IP to support a new command and data protocol. The previous IP supported 3-channels while the new will support 7 channels.
- The SPI can be daisy-chained, allowing multiple DUTs to talk to a single Host uC SPI Initiator.
Posted 16 Mar 2026 · Listing from OnJob.io. Create a free profile to apply and see your AI match score.
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