Lead IC Package Design Engineer

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Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests

You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day

Role: Lead Package Design Engineer

Experience: 10+ years-15 years Equivalent- Relevant

Education: BE/BTech or MTech in Electrical / Electronics Engineering Equivalent or Relavent

Role Summary

We are seeking an experienced IC Package Design Engineer with strong expertise in flip‑chip package design and IC‑Package‑PCB co‑design, focusing on signal integrity (SI), power integrity (PI), and thermal optimization. The role requires close collaboration with cross‑functional teams and customers to deliver optimized, cost‑effective, and high‑performance package solutions.

Key Responsibilities

• Lead flip‑chip package design with a strong focus on SI/PI and thermal constraints.
• Drive IC–Package–PCB co‑design, balancing performance, power, cost, technology, and thermal trade‑offs.
• Collaborate closely with cross‑functional teams and customers to define and deliver optimal end‑to‑end solutions.
• Support die floorplanning, IO placement and Perform bump definition, routing feasibility analysis, and optimization of Package stack‑up, BGA ball map and PCB design interfaces
• Execute 2D/3D EM simulations and apply electromagnetic and transmission line theory to package design challenges.
• Extract and analyze S‑parameters and RLGC models to ensure package compliance with SI/PI requirements.
• Validate package and PCB designs in the lab, correlating measurements with simulation results.
• Provide clear, concise program status updates to management, highlighting risks, issues, and mitigation plans.
• Drive process improvements, methodology development, innovation, and efficiency gains in package design flows.
• Mentor and support team members while contributing as an individual technical expert.
• Experience with various Cadence Allegro tools (APD/SIP, PCB Editor)
• Experience with various modeling tools (Cadence Sigrity PowerSI, ExtractIM, Clarity 3D)
• Experience in working with different DRAM protocols, DDR4/5, GDDR6/7, HBM3/4, LPDDR5/6
• Strong understanding of package cost vs. performance trade‑offs
• Proven ability to work independently and in cross‑functional teams
• Highly motivated, proactive, and eager to continuously acquire new skills

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