Principal DFT Design Engineer
Cadence
Principal DFT Design Engineer at Cadence is a full time role based in BANGALORE, India. It was published on 23 February 2024 and was open at last check.
| Role | Principal DFT Design Engineer |
|---|---|
| Company | Cadence |
| Location | BANGALORE, India |
| Employment type | Full Time |
| Published | 23 February 2024 |
| Status | Open at last check |
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- This role requires close interaction with multiple cross functional teams across geographies to align on project receivables/deliverables.
- Mentoring junior engineers and driving innovation/automation.
- BE/B.Tech/M.E/M.Tech with 7+ years of relevant work experience and strong understanding of DFT concepts and good communication skills.
- Strong hands-on experience using industry standard EDA Tools.
- Experience with logic simulators from one or more EDA vendors.
- Experience on industry standard ATPG tools like Cadence Modus.
- Experience with RTL lint tools like Jasper.
- Experience in scan insertion, coverage analysis and debugging skills on faults coverage enhancement is required.
- Programming in Perl/Tcl/Python or other scripting languages is a plus.
- Experience in post silicon validation, ATE debug and support is desired.
- Exposure to RTL2GDS flow and tasks such as synthesis and scan insertion, STA and IR drop.
- Good understanding of Logic design, RTL implementation & verification, logic synthesis, Logic Equivalent Checking & Static Timing Analysis are plus.
- Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability.
We’re doing work that matters. Help us solve what others can’t.
Create your free OnJob profile to apply — we'll take you to Cadence's application after sign-up. · Posted 23 Feb 2024.
Principal DFT Design Engineer at Cadence — questions answered
What does the Principal DFT Design Engineer role at Cadence pay?
Cadence does not publish a salary on this Principal DFT Design Engineer listing, so OnJob shows no figure for it rather than an estimate. For what this role pays across the market, the OnJob salary guides aggregate the live listings that do disclose pay.
Where is the Principal DFT Design Engineer role at Cadence based?
Cadence lists this Principal DFT Design Engineer role in BANGALORE, India, advertised as full time work at that location. Larger employers sometimes cover several sites under one city name, so confirm the exact office with Cadence before you apply.
Is the Principal DFT Design Engineer role at Cadence still open?
The Principal DFT Design Engineer posting at Cadence was open at OnJob's last check of the employer's careers page, having been published on 23 February 2024. OnJob re-checks source listings on each build and marks a role closed once it disappears, but listings can close without notice, so the employer's own page is the final word.
How do you apply for the Principal DFT Design Engineer role at Cadence?
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