Design Engineering Architect
Cadence
Design Engineering Architect at Cadence is a full time role based in CORK 01, Ireland. It was published on 14 May 2026 and was open at last check.
| Role | Design Engineering Architect |
|---|---|
| Company | Cadence |
| Location | CORK 01, Ireland |
| Employment type | Full Time |
| Published | 14 May 2026 |
| Status | Open at last check |
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.
Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Title: Design Engineering Architect
Location: Cork/Dublin, Ireland
Reports to: Design Engineering Director
Job Overview:
The Cadence Silicon Solutions Group (SSG) develop leading edge Intellectual Property (IP) for a variety of High-Tech Markets. The Cadence IP solutions allow our Customers to tackle IP-to-SoC development in a system context, enabling them to focus on product differentiation and to reduce time to volume.
The Cadence IP Vision is to deliver industry leading IP solutions to enable our customers to be successful across these fast-moving application spaces.
The Design Engineering Architect will be based in Cork, as part of an experienced Controller IP Team with long established IP development sites in Europe, US and India.
Job Responsibilities:
- Technical leadership of complex IP such as UCIe, Ethernet, HBM and PCIe.
- Collaborate with system architects and product managers to define the architecture and specifications on standards such as UCIe, considering factors such as data rate, power consumption, and compatibility with industry standards.
- Hands-on leadership of RTL development from micro-architecture definition to IP sign-off for general release.
- Contribute to planning of activities and milestones for the digital development teams.
- Leadership of cross-functional technical meetings with Analog & Software counterparts.
- Support customer pre-sales and post-sales meetings.
- Develop, maintain and improve upon processes and procedures for efficient product execution, IP quality and industry best practices.
- Participate in Technical Review Meetings and Checklist Reviews as part of ISO-9001.
- Represent Cadence in Standards Body Working Groups e.g. IEEE, PCI-SIG, JEDEC, UCIe
- Represent Cadence by presenting at Industry Conference such as IEEE, DAC.
Job Qualifications:
- Degree in Electrical/Electronic Engineering, microelectronics, or a related discipline.
- 15-20 years’ experience in microelectronics industry.
- Expert in Verilog/SystemVerilog RTL design essential.
- Expert in front-end design tools covering LINT, synthesis, CDC/RDC analysis essential.
- Experience of SoC architecture and development essential.
- Experience of technical team leadership essential.
- Excellent oral and written English essential.
- Self-motivated with excellent planning, interpersonal and with the ability to communicate complex concepts clearly and thoroughly.
Additional Skills/Preferences:
- Experience of Metric Driven Verification (MDV) and UVM desired.
- Experience of industry standard protocols such as AXI, CHI-C2C & CXS.B preferred.
- Experience of quality processes, such as ISO-9001 & ISO-26262 preferred.
Additional Information:
Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
Travel: <10%
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Create your free OnJob profile to apply — we'll take you to Cadence's application after sign-up. · Posted 14 May 2026.
Design Engineering Architect at Cadence — questions answered
What does the Design Engineering Architect role at Cadence pay?
Cadence does not publish a salary on this Design Engineering Architect listing, so OnJob shows no figure for it rather than an estimate. For what this role pays across the market, the OnJob salary guides aggregate the live listings that do disclose pay.
Where is the Design Engineering Architect role at Cadence based?
Cadence lists this Design Engineering Architect role in CORK 01, Ireland, advertised as full time work at that location. Larger employers sometimes cover several sites under one city name, so confirm the exact office with Cadence before you apply.
Is the Design Engineering Architect role at Cadence still open?
The Design Engineering Architect posting at Cadence was open at OnJob's last check of the employer's careers page, having been published on 14 May 2026. OnJob re-checks source listings on each build and marks a role closed once it disappears, but listings can close without notice, so the employer's own page is the final word.
How do you apply for the Design Engineering Architect role at Cadence?
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