Lead Design Engineer
Cadence
Lead Design Engineer at Cadence is a full time role based in HYDERABAD 04, India. It was published on 10 April 2024 and was open at last check.
| Role | Lead Design Engineer |
|---|---|
| Company | Cadence |
| Location | HYDERABAD 04, India |
| Employment type | Full Time |
| Published | 10 April 2024 |
| Status | Open at last check |
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description:
- To develop & integrate foundry rule decks & technology files to support PDKs by using foundry provided process design kits as a starting point.
- PDK QA, verification and release methodology for decks and specialized setups including track patterns to aid in layout.
- Responsible for physical verification methodology, including installation, development, qualification, automation, and support – To develop scripts to automate LVS, DRC, RM,IR and Parasitic Extraction flows.
- And to support layout teams in verification flow issues.
- Ensuring QA of the integrated PDK’s with the custom design environment Add sub scripts to improve efficiency on QA process with adequate coverage.
- General tool usage support – real-time support of all tools, creating bug workarounds and filing CCRs with R&D
- Responsible for rule deck development - to implement process design rules into physical verification rules decks and QC for the rule decks.
- Responsible for interfacing with the design teams and foundry team to develop and verify our PDKs.
- Develop, own and maintain an automation frame work for efficiency improvement perspective for the design environment.
Position Requirements:
- Bachelor’s Degree in Electrical/Electronic Engineering or equivalent .
- 4-7 years of Work experience in PDK development and CAD enablement.
- Expertise in Cadence Python, SKILL, Perl programming languages.
- Knowledge of deep sub-micron CMOS processes, device physics and layout design.
- Experience with Cadence custom IC Virtuoso platform to create layout test structures, to validate verification rules and to troubleshoot errors.
- Experience in developing PDK device library components and definitions including SKILL parameterized cells (Pcell), symbols, CDF, callbacks, simulation/netlisting.
- Experience with physical verification tools for DRC, LVS and parasitic extraction, Cadence PVS, Assura is a plus.
- Working knowledge of revision control software (Git, sos, Subversion, Synchronicity, etc)
- Understanding on Pcell creation and enhancements to pcell parameters, device call backs etc is a plus
- Excellent technical problem solving skills.
- Excellent communication and presentation skills.
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Create your free OnJob profile to apply — we'll take you to Cadence's application after sign-up. · Posted 10 Apr 2024.
Lead Design Engineer at Cadence — questions answered
What does the Lead Design Engineer role at Cadence pay?
Cadence does not publish a salary on this Lead Design Engineer listing, so OnJob shows no figure for it rather than an estimate. For what this role pays across the market, the OnJob salary guides aggregate the live listings that do disclose pay.
Where is the Lead Design Engineer role at Cadence based?
Cadence lists this Lead Design Engineer role in HYDERABAD 04, India, advertised as full time work at that location. Larger employers sometimes cover several sites under one city name, so confirm the exact office with Cadence before you apply.
Is the Lead Design Engineer role at Cadence still open?
The Lead Design Engineer posting at Cadence was open at OnJob's last check of the employer's careers page, having been published on 10 April 2024. OnJob re-checks source listings on each build and marks a role closed once it disappears, but listings can close without notice, so the employer's own page is the final word.
How do you apply for the Lead Design Engineer role at Cadence?
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