Sr. Principal Engineer, RTL ASIC Design
Marvell
Sr. Principal Engineer, RTL ASIC Design at Marvell is a full time role based in Hyderabad, India. It was published on 9 July 2026 and was open at last check.
| Role | Sr. Principal Engineer, RTL ASIC Design |
|---|---|
| Company | Marvell |
| Location | Hyderabad, India |
| Employment type | Full Time |
| Published | 9 July 2026 |
| Status | Open at last check |
About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
What You Can Expect
- Define the SoC, sub system architecture, micro-architecture and register specification for highly complex SoCs. Drive and participate in specification writeup
- Work closely with system and chip architects to design industrial quality implementations.
- Conduct detailed performance, architectural and design requirement reviews with cross-functional teams, IP Vendors and customers
- Implement a specification using RTL coding techniques and best practices
- Work with third party vendors to define customization requirements of third party IPs (controller, PHY, etc.)
- Work with the physical design teams, reviewing and providing guidance in floorplanning, power analysis, synthesis and timing signoff.
- Work with the verification team on pre-silicon verification tasks such as reviewing the verification test plans, coverage analysis, full-chip simulation and emulation, performance and power analysis and debug
- Help develop and/or evaluate design and verification methodology
What We're Looking For
- Bachelor’s/Masters degree in Computer Science, Electrical Engineering or related fields and 18+ years of related professional experience. PhD in Computer Science, Electrical Engineering or related fields with 16+ years of experience.
- Architect and design SoC, subsystems (reset, boot, power, security, access control, debug, CPU, DSP, AI accelerators).
- Define specifications, microarchitecture, and use cases with cross-functional teams.
- Collaborate with hardware, firmware, and security teams to ensure design efficiency.
- Perform trade-off analysis (area, power, performance, security, HW/SW reusability).
- Work on high-speed interconnects (PCIe, CXL, DDR) and system caches.
- Strong experience in SoC architecture, HW microarchitecture, and security.
- Expertise in ARM-based SoC architectures, including compute, memory management, and virtualization.
- Knowledge of high/low-speed peripherals, DDR, interconnects, QoS, and power management.
- Experience in performance analysis, simulation, modeling, and VLSI design flow.
- Proficiency in HDL, scripting, and digital design.
- Strong communication and collaboration skills for global teams.
Additional Compensation and Benefit Elements
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
Create your free OnJob profile to apply — we'll take you to Marvell's application after sign-up. · Posted 9 Jul 2026.
Sr. Principal Engineer, RTL ASIC Design at Marvell — questions answered
What does the Sr. Principal Engineer, RTL ASIC Design role at Marvell pay?
Marvell does not publish a salary on this Sr. Principal Engineer, RTL ASIC Design listing, so OnJob shows no figure for it rather than an estimate. For what this role pays across the market, the OnJob salary guides aggregate the live listings that do disclose pay.
Where is the Sr. Principal Engineer, RTL ASIC Design role at Marvell based?
Marvell lists this Sr. Principal Engineer, RTL ASIC Design role in Hyderabad, India, advertised as full time work at that location. Larger employers sometimes cover several sites under one city name, so confirm the exact office with Marvell before you apply.
Is the Sr. Principal Engineer, RTL ASIC Design role at Marvell still open?
The Sr. Principal Engineer, RTL ASIC Design posting at Marvell was open at OnJob's last check of the employer's careers page, having been published on 9 July 2026. OnJob re-checks source listings on each build and marks a role closed once it disappears, but listings can close without notice, so the employer's own page is the final word.
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