Principal Design Engineer
Cadence
Principal Design Engineer at Cadence is a full time role based in PUNE, Belgium. It was published on 6 November 2024 and was open at last check.
| Role | Principal Design Engineer |
|---|---|
| Company | Cadence |
| Location | PUNE, Belgium |
| Employment type | Full Time |
| Published | 6 November 2024 |
| Status | Open at last check |
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Performance Modeling Engineer
Location – India (Pune)
Summary
We are looking for modeling engineers to help develop performance models, perform architectural tradeoff analysis, and enable data driven design decisions for our next generation DDR memory controller architectures that can meet today’s complex SoC and workload requirements. Hardware modelling experience (C++/SystemC/TLM/Python) and computer architecture foundation is desired.
Responsibilities
- Develop cycle-level performance models in SystemC or C++
- Correlate performance models to match RTL configurations and traffic conditions
- Work with Memory Architects to understand feature requirements, architectural specifications and implement in the model
- Analyze architectural trade-offs (throughput, hardware cost) across different scenarios and architectural choices
- Develop synthetic memory traffic/traces that are representative of real-world applications (CPU, GPU, DSP, NoC, etc)
- Develop scripts to automate generation of various performance metrics and statistics post RTL simulation that helps identify performance bottlenecks
Required Skills
- BE/B.Tech ME/M.Tech in ECE, E&TC, CS or similar
- 8+ years of experience in hardware modeling, functional or performance
- Strong coding skills in C++, SystemC and Transaction Level Modeling (TLM)
- Basic understanding of performance principles, Queuing Theory, throughput/latency tradeoffs
Additional Skills
- Understand RTL-Verilog, SV, UVM and experience analyzing waveforms
- Understand memory protocols and timing – DDR4, DDR5, LP4, LP5
- Experience using performance simulators – Memory Controller, NoC, CPU models
- Coding in Python and familiarity with packages like Pandas, Matplotlib
- Experience working with performance benchmarks – SPEC, STREAM, etc
- Concepts related to Quality of Service (QoS) and how memory controller can tradeoff performance and latencies
We’re doing work that matters. Help us solve what others can’t.
Create your free OnJob profile to apply — we'll take you to Cadence's application after sign-up. · Posted 6 Nov 2024.
Principal Design Engineer at Cadence — questions answered
What does the Principal Design Engineer role at Cadence pay?
Cadence does not publish a salary on this Principal Design Engineer listing, so OnJob shows no figure for it rather than an estimate. For what this role pays across the market, the OnJob salary guides aggregate the live listings that do disclose pay.
Where is the Principal Design Engineer role at Cadence based?
Cadence lists this Principal Design Engineer role in PUNE, Belgium, advertised as full time work at that location. Larger employers sometimes cover several sites under one city name, so confirm the exact office with Cadence before you apply.
Is the Principal Design Engineer role at Cadence still open?
The Principal Design Engineer posting at Cadence was open at OnJob's last check of the employer's careers page, having been published on 6 November 2024. OnJob re-checks source listings on each build and marks a role closed once it disappears, but listings can close without notice, so the employer's own page is the final word.
How do you apply for the Principal Design Engineer role at Cadence?
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