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Senior Manager, System Integration – Silicon Co-Design Group

NVIDIA

Santa Clara, United States of AmericaFull Time

Senior Manager, System Integration – Silicon Co-Design Group at NVIDIA is a full time role based in Santa Clara, United States of America. It was published on 28 July 2026 and was open at last check.

Senior Manager, System Integration – Silicon Co-Design Group at NVIDIA — key details
RoleSenior Manager, System Integration – Silicon Co-Design Group
CompanyNVIDIA
LocationSanta Clara, United States of America
Employment typeFull Time
Published28 July 2026
StatusOpen at last check

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. System Integration sits at the intersection of all of them. It is the layer where every architecture, design, software, and manufacturing decision meets reality. When something breaks late in a program, it usually breaks here first.

We are hiring a Senior Manager to lead this team in the US and partner closely with teams globally. Your work will sit on the critical path of every NVIDIA silicon program, and the bar you set for system integration is the bar we ship to! The two hardest, highest-leverage problems in this seat:

  • Find critical silicon issues earlier — often before software is production-ready. Left-shifting post-silicon coverage is the highest-value thing System Integration can do. Standing up wide-area testing as a repeatable capability is a core part of the role.
  • Keep programs on milestone when upstream dependencies slip. Validation plans collide with reality every program! The team needs new strategies, not just contingency plans, to keep moving when software, firmware, or methodology slip. You will design and run those strategies.

What you’ll be doing:

  • Plan and execute post-silicon feature integration, PVT validation, and wide-area testing across NVIDIA’s GPU, SoC, and CPU programs.
  • Build wide-area and in-system test as a repeatable capability that shifts post-silicon coverage left, so issues surface before we are production-ready.
  • Lead resolution of the most complex system-level issues, RMAs, and HW/SW interaction problems with creative workarounds and focused lab experimentation.
  • Develop new strategies to keep programs on milestone when upstream dependencies — software, firmware, methodology, validation — slip.
  • Hire, mentor, and retain senior technical talent. Build a strong bench and grow individual contributors into the next generation of senior technical leaders.
  • Partner across architecture, design, DFT, software, firmware, QA, and manufacturing teams.
  • Build operational rigor — bring-up tracking, debug forums, and a clear translation of execution data into structured, decision-ready options.

What we need to see:

  • Bachelor’s or Master’s in Electrical or Computer Engineering (or equivalent experience), plus over 12+ overall years of system-level post-silicon bring-up and debug experience, including 5 years leading technical teams, with shipped silicon.
  • Direct experience finding critical silicon issues before software was production-ready — including building or scaling wide-area or in-system test programs that ran in production.
  • Led technical teams across multiple geographies, with clear examples of attracting, growing, and retaining senior technical talent.
  • Strong EE fundamentals across DFT, digital design, computer architecture, power, timing, and fault analysis, plus the ability to translate complex technical issues into clear options for executive audiences.

Ways to stand out from the crowd:

  • A history of process and methodology improvements that meaningfully lifted bring-up velocity, debug efficiency, or shipped silicon quality on programs you led.
  • Experience partnering deeply with a counterpart team in India or another major engineering hub — examples of building shared culture, shared metrics, and shared on-call across geographies.
  • DFT experience with system-test features for in-field test on production silicon, plus familiarity with fault models, DPPM, quality metrics, and RAS.
  • Concrete examples of redesigning how a team works with AI — faster analysis, smarter debug, automated reporting, or workflows the team adopted broadly.

NVIDIA is the world leader in accelerated computing, and our work powers AI, gaming, robotics, autonomous systems, and scientific discovery. We invest in our people with competitive benefits, flexible time off, and continuous learning, and we build a team where everyone can do their best work.

You will also be eligible for equity and benefits.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

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Create your free OnJob profile to apply — we'll take you to NVIDIA's application after sign-up. · Posted 28 Jul 2026.

Senior Manager, System Integration – Silicon Co-Design Group at NVIDIA — questions answered

What does the Senior Manager, System Integration – Silicon Co-Design Group role at NVIDIA pay?

NVIDIA does not publish a salary on this Senior Manager, System Integration – Silicon Co-Design Group listing, so OnJob shows no figure for it rather than an estimate. For what this role pays across the market, the OnJob salary guides aggregate the live listings that do disclose pay.

Where is the Senior Manager, System Integration – Silicon Co-Design Group role at NVIDIA based?

NVIDIA lists this Senior Manager, System Integration – Silicon Co-Design Group role in Santa Clara, United States of America, advertised as full time work at that location. Larger employers sometimes cover several sites under one city name, so confirm the exact office with NVIDIA before you apply.

Is the Senior Manager, System Integration – Silicon Co-Design Group role at NVIDIA still open?

The Senior Manager, System Integration – Silicon Co-Design Group posting at NVIDIA was open at OnJob's last check of the employer's careers page, having been published on 28 July 2026. OnJob re-checks source listings on each build and marks a role closed once it disappears, but listings can close without notice, so the employer's own page is the final word.

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