Design Engineer II
Cadence
Design Engineer II at Cadence is a full time role based in BANGALORE, India. It was published on 1 September 2026 and was open at last check.
| Role | Design Engineer II |
|---|---|
| Company | Cadence |
| Location | BANGALORE, India |
| Employment type | Full Time |
| Published | 1 September 2026 |
| Status | Open at last check |
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The role will be a key player in organization responsible for Characterizing and validating Analog and Digital IP based Silicon Solutions at Cadence.
Candidate should possess strong leadership skills with ability to manage multiple priorities and guide team members on day-to-day lab tests and silicon characterization activities. Ownership of tasks, ability to collaborate with remote teams located worldwide and clear communication skills, are must have attributes in this role. Coordination with R&D, Marketing teams in defining the scope and delivering the results in time are critical.
Minimum Qualifications & Professional Experience:
- 2-10years (with BTech) or 10 years (with MTech) experience in Post-Silicon PHY, Systems Interop and Compliance testing.
- 5-7 years of management experience leading/mentoring a small team of engineers
- Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on Ethernet/PCIe/CXL/UCIe/
- Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers.
- Proficient with Ethernet, PCIe, UCIe standards and Protocols. Proven experience to interpret the standard’s specification to develop Electrical and Protocol, Interoperability and Compliance test suites to validate the silicon.
- Ability to isolate the PHY and controller (MAC/PCS) features to test, develop calibration / compliance lab suites and characterize.
- Architect and design Printed circuit boards in Schematic and layout level. Familiarity with peripheral chips, high speed interface design techniques, Signal and Power integrity checks / analysis and fixes needed to meet the performance requirements.
- Experience in PCIe/UCIe LTSSM states / UCIe Interfaces / Ethernet standards is a plus.
- Proven experience in developing lab automation scripts and test result analysis to debug and root cause silicon failures.
- Expertise in developing ESD/Latchup/ HTOL tests to meet industry standards reliability qualification & specification
- Expert level knowledge in Verilog RTL coding for FPGA, python,C/C++
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Create your free OnJob profile to apply — we'll take you to Cadence's application after sign-up. · Posted 1 Sept 2026.
Design Engineer II at Cadence — questions answered
What does the Design Engineer II role at Cadence pay?
Cadence does not publish a salary on this Design Engineer II listing, so OnJob shows no figure for it rather than an estimate. For what this role pays across the market, the OnJob salary guides aggregate the live listings that do disclose pay.
Where is the Design Engineer II role at Cadence based?
Cadence lists this Design Engineer II role in BANGALORE, India, advertised as full time work at that location. Larger employers sometimes cover several sites under one city name, so confirm the exact office with Cadence before you apply.
Is the Design Engineer II role at Cadence still open?
The Design Engineer II posting at Cadence was open at OnJob's last check of the employer's careers page, having been published on 1 September 2026. OnJob re-checks source listings on each build and marks a role closed once it disappears, but listings can close without notice, so the employer's own page is the final word.
How do you apply for the Design Engineer II role at Cadence?
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