ASIC Verification Engineer - Clocks
NVIDIA
ASIC Verification Engineer - Clocks at NVIDIA is a full time role based in Bengaluru, India. It was published on 4 September 2026 and was open at last check.
| Role | ASIC Verification Engineer - Clocks |
|---|---|
| Company | NVIDIA |
| Location | Bengaluru, India |
| Employment type | Full Time |
| Published | 4 September 2026 |
| Status | Open at last check |
The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA Clocks Team is committed to deliver high-quality clocking and reset logic to various units in SOC automotive and datacenter ASICs. The complexity of the clocks and resets design has increased many folds. This requires sophisticated verification to deliver a bug free clocks/resets design to power our product lines ranging from Data Centers, Consumer graphics to Self-driving cars and the growing field of artificial intelligence. Modern clocking verification solutions need to be innovative, ensure quality in covering the complex design specifications and balance the constraints on infrastructure, re-usability, testing speed and multi-platform support.
What you'll be doing:
- Own validation of Clocking structures in Tegra automotive and datacenter products from start to finish, including test plan development, automation, validation flows development, coverage metrics, test execution, bug identification/fix and productization.
- Tackle Sophisticated problems and develop a scalable solution that works across platform.
- Hands on industry-standard tools and state of the art verification methodologies. This includes coding in System Verilog, UVM, C++, Perl, Python and NVIDIA custom compilers and tools.
- Partnering closely with our clocks/reset architecture and design team to validate our clocks/reset design.
- Coordinate with internal and external teams across time zones.
What we need to see:
- BS or MS in EE/ECE or equivalent experience.
- 2+ years of relevant industry work experience.
- Good understanding of Logic Design and Architecture.
- Expertise in industry-standard verification flows like SV constraint random verification, UVM, Formal Verification, Coverage metrics, profiling tools, X prop, etc.
- Exposure on block level and system-level verification.
- Strong coding skills in System Verilog, scripting languages (Perl/python) and C++.
- Ability to collaborate and work with multiple groups.
- Prior experience in implementing Test plans for pre-silicon platforms.
- Understanding of DFT/IST is optional.
We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our world-class engineering teams are growing fast. If you are creative, curious, and motivated with real passion for technology, we want to hear from you!
#LI-Hybrid
Create your free OnJob profile to apply — we'll take you to NVIDIA's application after sign-up. · Posted 4 Sept 2026.
ASIC Verification Engineer - Clocks at NVIDIA — questions answered
What does the ASIC Verification Engineer - Clocks role at NVIDIA pay?
NVIDIA does not publish a salary on this ASIC Verification Engineer - Clocks listing, so OnJob shows no figure for it rather than an estimate. For what this role pays across the market, the OnJob salary guides aggregate the live listings that do disclose pay.
Where is the ASIC Verification Engineer - Clocks role at NVIDIA based?
NVIDIA lists this ASIC Verification Engineer - Clocks role in Bengaluru, India, advertised as full time work at that location. Larger employers sometimes cover several sites under one city name, so confirm the exact office with NVIDIA before you apply.
Is the ASIC Verification Engineer - Clocks role at NVIDIA still open?
The ASIC Verification Engineer - Clocks posting at NVIDIA was open at OnJob's last check of the employer's careers page, having been published on 4 September 2026. OnJob re-checks source listings on each build and marks a role closed once it disappears, but listings can close without notice, so the employer's own page is the final word.
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