Senior Principal HW/SW Co-Design Lead
NXP Semiconductors
Senior Principal HW/SW Co-Design Lead at NXP Semiconductors is a full time role based in Pune, India. It was published on 22 April 2026 and was open at last check.
| Role | Senior Principal HW/SW Co-Design Lead |
|---|---|
| Company | NXP Semiconductors |
| Location | Pune, India |
| Employment type | Full Time |
| Published | 22 April 2026 |
| Status | Open at last check |
This role is a technical leader that bridges between HW and SW to ensure world-class solutions for our customers. This role resides and works alongside the HW team to reuse and develop low level drivers and application to be a bridge to central SW team. Responsible for ensuring high quality HW drivers to take full advantage of HW features and make them available via the SDK to customers (internal and external). This role will drive HW-SW to ensure consistency, early verification of drivers, combined use-cases and ROM features in simulation and in emulation before silicon tape out. The role will also ensure that product verification (SW + HW teams) and all validation teams are enabled with the same drivers for validation of the product.
Job Responsibility:
- Technical lead for given SOC products in developing low‑level IP firmware (device drivers) for MCU platforms, ensuring high quality and reusability. Work closely with central SW teams to maximize reuse, consistency and ensure HW compatibility.
- Architect and deliver comprehensive IP firmware/driver solutions that support all phases of the lifecycle—RTL verification, virtual simulation, SoC verification, post‑silicon validation, and SDK integration
- Partner with pre‑silicon and post‑silicon teams to align HAL/SDK development with IP interface requirements and features.
- Work closely with HW, SW architects and SOC designers to initiate firmware development in parallel with hardware development.
- Review hardware register definitions and documentation early and regularly to remove disconnects and provide actionable feedback to improve software usability and long‑term maintainability. This role owns any gap closure.
- Establish and maintain backward‑compatible software interfaces as hardware IP evolves across products. Ensure linkage with HW IP and central SW team.
- Create architectural frameworks that promote consistency and scalability of driver implementations.
- Define best practices for delivering enablement drivers alongside hardware IP, ensuring smooth integration into SoC platforms and customer SDKs.
- Support multiple execution environments—simulation, emulation, and silicon—to ensure robust API behavior.
- Champion quality practices including design reviews, code reviews, static analysis, and adherence to coding standards.
- Produce clear, comprehensive technical documentation, reports, and presentations for stakeholders and milestone reviews.
- Use Git, JIRA, and Confluence to drive project execution, collaboration, and traceability.
- Mentor and guide junior and mid‑level software engineers, providing technical leadership and fostering a collaborative team environment.
- Contribute to ongoing optimization of firmware development workflows, tools, and cross‑team processes.
Job Qualification:
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.
- Experience in RTL simulation and emulation. Must be able to understand how SOC’s are built and be able to work with RTL, HW and SW verification environments.
- Minimum of 15 years of experience in architecture and/or firmware development for MCUs/MPUs.
- Deep expertise in MCU/MPU SW architecture and low‑level firmware development, including RTL bring‑up, driver design, and platform‑level integration.
- Ability to lead by influence and bring cross‑functional teams together to accomplish goals.
- Experience leveraging AI capabilities to accelerate software development and documentation.
- Proficiency with ARM processor subsystems, tools, and debugging methodologies.
- Experience working with embedded RTOS and compilers.
- Competence in low‑level software testing and debugging for MCUs and MPUs.
- Ability to work in a multi‑site, multi‑time‑zone environment.
- Proficiency in C/C++/Assembly languages and at least one scripting language.
- Excellent problem‑solving, analytical, and debugging skills.
- Strong communication and interpersonal skills, with the ability to effectively collaborate with cross‑functional teams and mentor junior engineers.
- Prior experience in a technical leadership role, driving projects and influencing technical direction is highly desirable.
Create your free OnJob profile to apply — we'll take you to NXP Semiconductors's application after sign-up. · Posted 22 Apr 2026.
Senior Principal HW/SW Co-Design Lead at NXP Semiconductors — questions answered
What does the Senior Principal HW/SW Co-Design Lead role at NXP Semiconductors pay?
NXP Semiconductors does not publish a salary on this Senior Principal HW/SW Co-Design Lead listing, so OnJob shows no figure for it rather than an estimate. For what this role pays across the market, the OnJob salary guides aggregate the live listings that do disclose pay.
Where is the Senior Principal HW/SW Co-Design Lead role at NXP Semiconductors based?
NXP Semiconductors lists this Senior Principal HW/SW Co-Design Lead role in Pune, India, advertised as full time work at that location. Larger employers sometimes cover several sites under one city name, so confirm the exact office with NXP Semiconductors before you apply.
Is the Senior Principal HW/SW Co-Design Lead role at NXP Semiconductors still open?
The Senior Principal HW/SW Co-Design Lead posting at NXP Semiconductors was open at OnJob's last check of the employer's careers page, having been published on 22 April 2026. OnJob re-checks source listings on each build and marks a role closed once it disappears, but listings can close without notice, so the employer's own page is the final word.
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