ASIC Design and STA Engineer
NVIDIA
ASIC Design and STA Engineer at NVIDIA is a full time role based in Bengaluru, India. It was published on 25 July 2026 and was open at last check.
| Role | ASIC Design and STA Engineer |
|---|---|
| Company | NVIDIA |
| Location | Bengaluru, India |
| Employment type | Full Time |
| Published | 25 July 2026 |
| Status | Open at last check |
NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!
NVIDIA is looking for a best-in-class ASIC STA Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency for today's AI platforms! Come and take a part in designing our groundbreaking large scale and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
- Be in charge of full chip and/or chiplet level STA convergence from early stages to signoff.
- Take part in top level floor plan and clock planning.
- Optimize, together with CAD signoff flows and methodologies.
- Digital Partitions' and analog IPs' timing integration, giving feedback to PD/RTL and driving convergence.
- Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including their optimization for runtime and efficiency.
What we need to see:
- B.SC./ M.SC. in Electrical Engineering/Computer Engineering.
- 3+ years of experience in physical design and STA
- Proven experience in RTL2GDS and STA design and convergence
- Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.)
- Hands on STA experience from early stages to signoff using Synopsis Primetime. Deep knowledge in timing concepts required.
- Great teammate.
NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!
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Create your free OnJob profile to apply — we'll take you to NVIDIA's application after sign-up. · Posted 25 Jul 2026.
ASIC Design and STA Engineer at NVIDIA — questions answered
What does the ASIC Design and STA Engineer role at NVIDIA pay?
NVIDIA does not publish a salary on this ASIC Design and STA Engineer listing, so OnJob shows no figure for it rather than an estimate. For what this role pays across the market, the OnJob salary guides aggregate the live listings that do disclose pay.
Where is the ASIC Design and STA Engineer role at NVIDIA based?
NVIDIA lists this ASIC Design and STA Engineer role in Bengaluru, India, advertised as full time work at that location. Larger employers sometimes cover several sites under one city name, so confirm the exact office with NVIDIA before you apply.
Is the ASIC Design and STA Engineer role at NVIDIA still open?
The ASIC Design and STA Engineer posting at NVIDIA was open at OnJob's last check of the employer's careers page, having been published on 25 July 2026. OnJob re-checks source listings on each build and marks a role closed once it disappears, but listings can close without notice, so the employer's own page is the final word.
How do you apply for the ASIC Design and STA Engineer role at NVIDIA?
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