Design Methodology – Principal DRAM Power Integrity Engineer
Micron
Design Methodology – Principal DRAM Power Integrity Engineer at Micron is a full time role based in Hyderabad - Phoenix Aquila, India. It was published on 9 April 2026 and was open at last check.
| Role | Design Methodology – Principal DRAM Power Integrity Engineer |
|---|---|
| Company | Micron |
| Location | Hyderabad - Phoenix Aquila, India |
| Employment type | Full Time |
| Published | 9 April 2026 |
| Status | Open at last check |
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Key Responsibilities:
- Develop and standardize EMIR methodology that applies consistently across all DRAM products, ensuring alignment, repeatability, and high-quality analysis outcomes
- Perform static and dynamic EM/IR and PDN analysis using RedHawk or Totem or other industry‑standard tools; identify root‑cause issues such as high‑resistance segments, insufficient via density, and decap deficiencies, and provide clear, actionable recommendations to design and layout teams.
- Actively leverage AI‑based tools, agentic workflows, and automation frameworks for effective Power-delivery-network (PDN) analysis.
- Maintain a strong understanding of the full EMIR flow—from netlist preparation, extraction, simulation, and debug to reporting and silicon correlation—and ensure accurate evaluation across operating modes and temperatures.
- Partner across design, timing, physical implementation, architecture, modeling, and verification teams to understand real switching behavior, develop worst‑case vectors, and standardize analysis expectations across global teams.
- Collaborate with cross-geographical teams and also EDA tool vendors to evaluate and improve EMIR methodologies, and document Best Known Methods (BKMs) to enhance consistency and correlation across DRAM teams.
- Develop and maintain dashboards to track EMIR results, monitor trends, and support signoff progression for multiple designs.
Qualifications:
- Master’s degree in electrical or computer engineering.
- 8 - 14 years of experience in PDN / Power Integrity / EMIR analysis for advanced semiconductor or SoC designs.
- Deep hands‑on experience with Ansys RedHawk or Totem for full‑chip EM/IR verification and PDN analysis, including setup, scenario creation, debug, and root‑cause analysis.
- Expertise in vectorless and dynamic/pattern‑based IR‑drop analysis, with strong ability to interpret current behavior, switching activity, and voltage‑sensitivity trends.
- Proven ability to identify root causes of IR‑drop issues—including switching activity, grid resistance, parasitics, routing topology—and translate analysis results into actionable design or layout fixes.
- Experience performing SoC‑level or chip‑level EMIR signoff and supporting tapeouts.
- Solid understanding of PDN interactions with circuit timing/margin, layout topology, and chip‑level power architecture.
- Ability to understand the full end‑to‑end design flow, including RTL, floorplanning, routing, extraction, EMIR, STA, and silicon correlation.
- Familiarity with Make or similar automation frameworks for EMIR rollups.
- Hands‑on experience with low‑power, multi‑voltage, power‑off, or mixed‑signal designs.
- Experience in chip‑level IR/EM analysis and driving closure across multi‑functional teams.
Preferred Qualifications:
- Experience with power‑modeling or current‑source modeling flows (e.g., CPM).
- Scripting skills in Python/Tcl for automation and data analysis.
- Experience in improving EMIR/PI analysis flows or methodology.
- Knowledge of PnR or STA tools (FusionCompiler, PrimeTime).
- Background in circuit design with SPICE experience.
- Exposure to or strong interest in AI/ML-assisted design flows, agentic AI or advanced automation in circuit design and verification.
- Familiarity with memory‑product power behavior (DRAM/SRAM/NAND).
About Micron Technology, Inc.
We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.
To learn more, please visit micron.com/careers
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.
To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
Create your free OnJob profile to apply — we'll take you to Micron's application after sign-up. · Posted 9 Apr 2026.
Design Methodology – Principal DRAM Power Integrity Engineer at Micron — questions answered
What does the Design Methodology – Principal DRAM Power Integrity Engineer role at Micron pay?
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Where is the Design Methodology – Principal DRAM Power Integrity Engineer role at Micron based?
Micron lists this Design Methodology – Principal DRAM Power Integrity Engineer role in Hyderabad - Phoenix Aquila, India, advertised as full time work at that location. Larger employers sometimes cover several sites under one city name, so confirm the exact office with Micron before you apply.
Is the Design Methodology – Principal DRAM Power Integrity Engineer role at Micron still open?
The Design Methodology – Principal DRAM Power Integrity Engineer posting at Micron was open at OnJob's last check of the employer's careers page, having been published on 9 April 2026. OnJob re-checks source listings on each build and marks a role closed once it disappears, but listings can close without notice, so the employer's own page is the final word.
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